Join the REACT Doctoral Network
Explore our open PhD positions in neuromorphic computing and intelligent systems.
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DC1: Secure neuromorphic architectures
Description: The objective of this project is to develop secure neuromorphic architectures by leveraging emerging memory technologies. Security primitives such as Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) will be investigated using Resistive RAM (RRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FeRAM), and Phase-Change Memory (PCM). These primitives will undergo comprehensive evaluation and benchmarking to assess their performance, reliability, and security. The most promising candidate will be selected for implementation through simulation, emulation, and hardware prototyping. Security properties will be analyzed at the device, circuit, and system levels to ensure robustness across the entire stack.
Supervisor(s): Farhad Merchant
Host institute: University of Groningen, The Netherlands
Contact person: Farhad Merchant, University of Groningen, The Netherlands,
Email: f.a.merchant@rug.nl
More details at the host webpage:
DC2: Novel FeRAM/FeFET-based neuromorphic architectures
Description: Ferroelectric RAM (FeRAM) leverages a ferroelectric layer in place of a conventional dielectric to achieve non-volatility. In contrast, the Ferroelectric Field-Effect Transistor (FeFET) is a MOSFET that incorporates a ferroelectric gate oxide, enabling non- volatile threshold voltage shifts. Both FeRAM and FeFET hold significant potential for neuromorphic computing applications. However, their adoption at the system level necessitates comprehensive investigation to assess their efficiency and effectiveness. This project aims to develop neuromorphic architectures based on FeRAM and FeFET technologies and benchmark their performance against state-of-the-art architectures to evaluate their feasibility for commercial deployment.
Supervisor(s): Farhad Merchant
Host institute: University of Groningen, The Netherlands
Contact person: Farhad Merchant, University of Groningen, The Netherlands,
Email: f.a.merchant@rug.nl
More details at the host webpage:
DC3: Novel magneto-resistive random access memory-based neuromorphic architectures
Description: Magnetoresistive devices operate based on the interaction between electron spin and magnetic fields, where the device resistance varies according to the relative orientation of magnetic layers. This project aims to investigate the suitability of magnetoresistive devices for neuromorphic computing applications, focusing on the development of energy-efficient neuromorphic architectures that can be emulated using these devices. A system-level simulation and FPGA-based emulation framework will be developed to evaluate the performance and energy efficiency of architectures incorporating magnetoresistive elements. Ultimately, various configurations will be benchmarked against state-of-the-art neuromorphic architectures to assess the feasibility of magnetoresistive devices in enabling future-generation, self-aware neuromorphic systems.
Supervisor(s): Farhad Merchant
Host institute: University of Groningen, The Netherlands
Contact person: Farhad Merchant, University of Groningen, The Netherlands,
Email: f.a.merchant@rug.nl
More details at the host webpage:
DC4: Energy-Efficient online learning using gain-cell memory-based compute-in-memory architecture
Description: The objective of this project is to develop a gain-cell memory-based compute-in- memory (CIM) architecture to enable energy-efficient online learning at the edge. Conventional edge devices are limited by constraints in power, latency, and memory bandwidth, which poses significant challenges to real-time learning when using traditional von Neumann architectures. By leveraging gain-cell memory, which offers high density and low leakage, and integrating mixed-signal computation directly into memory arrays, the proposed approach significantly reduces data movement and energy consumption. To ensure dependable operation under real- world conditions, efficient fault detection and recovery mechanisms will also be evaluated and integrated, addressing the susceptibility of analog and in-memory computing to noise, process variation, and soft errors.
Supervisor(s): Manil Dev Gomony
Host institute: TU Eindhoven, The Netherlands
Contact person: Manil Dev Gomony,
Email: m.gomony@tue.nl
More details at the host webpage:
DC5: Design tools, models and circuits for neuromorphic computing
Description: Neuromorphic computing is transforming energy-efficient hardware with architectures inspired by the brain. Memristive devices, especially Resistive RAM (ReRAM), offer analog computation at the sensor level, enabling ultra-low-power processing. Crossbar arrays built from these devices allow highly parallel, scalable computation ideal for edge AI. However, current design tools remain limited—while simulators exist, no synthesis framework integrates analog and digital layers for memristive neuromorphic systems. Bridging this gap is essential to unlocking the full potential of brain-inspired computing and creating the next generation of intelligent, energy-efficient machines. This challenge presents a unique opportunity to shape the future of hardware and AI.
Supervisor(s): Shahar Kvatinsky
Host institute: Technion – Israel Institute of Technology, Israel
Contact person: Shahar Kvatinsky,
Email: shahar@ee.technion.ac.il
More details at the host webpage:
DC6: Adaptive mixed-signal neuromorphic hardware accelerator
Description: This project aims to design and experimentally demonstrate a reconfigurable neuromorphic hardware accelerator that can adapt its resolution from binary to multi-bit precision. It will cover a full design cycle—from architecture definition to prototyping in CMOS technology— with emphasis on energy efficiency, scalability, and adaptability. The project will leverage advanced analog/mixed-signal techniques, focusing on energy-efficient data converters and time-domain processing to enable flexible and efficient neural computation.
Supervisor(s): Nicolás Wainstein
Host institute: Technion – Israel Institute of Technology, Israel
Contact person: Nicolás Wainstein,
Email: nicolasw@ef.technion.ac.il
More details at the host webpage:
DC7: Programming models and high-level compilation for near-sensor dataflow execution under security constraints
Description: This project investigates novel programming models and compilation methodologies for reactive applications that execute close or at sensing nodes in cyber-physical systems (CPS). We built on prior work on MLIR to create a code generation framework that optimises not only for performance and energy efficiency, but also for reliability and security concerns identified in the REACT Doctoral Network. In this way, dataflow and streaming applications can be efficiently, automatically and safely deployed in emerging distributed CPSs. In this context, we will devise novel methods to decide when to offload computation to in- memory neuromorphic accelerators close to sensing nodes. This will be achieved transparently from high-level programming abstractions, thus boosting the programming productivity in the otherwise extremely challenging area of programming distributed CPS.
Supervisor(s): Jeronimo Castrillon
Host institute: TU Dresden, Germany
Contact person: Jeronimo Castrillon,
Email: jeronimo.castrillon@tu-dresden.de
More details at the host webpage:
DC8: Towards true and reliable analog resistive switching in 1T1R CMOS-compatible RRAM devices
Description: To ensure high accuracy and to improve performance over tradition digital hardware in terms of area and energy consumptions, RRAM-based accelerators must reliably store multiple resistive states in their 1T1R cells. The PhD candidate will work on programming CMOS-compatible RRAM devices, targeting maximum multi-level capability. This will involve research on fabrication, device design, and programming algorithms. The candidate will also carry out electrical characterization to test and compare the throughput of different solutions. Once reliable devices are identified, additional work will focus on modeling and integrating them into IHP’s Process Design Kit (PDK) to support neuromorphic circuit development.
Supervisor(s): Christian Wenger
Host institute: Leibniz Institute for High Performance Microelectronics (IHP), Germany
Contact person: Christian Wenger, Tommaso Rizzi,
Email: wenger@ihp-microelectronics.com,
rizzi@ihp-microelectronics.com
More details at the host webpage:
DC9: Formal Verification for approximate in-memory computing
Description: This project focuses on the formal verification of approximate designs for In- Memory Computing (IMC) systems. While approximate computing offers significant gains in power, performance, and area, it must still adhere to specific error bounds and functional specifications to maintain desired output quality. IMC designs pose unique challenges due to their flattened structure and lack of architectural information. We aim to develop tailored methods to verify that IMC circuits meet their error constraints and functional correctness. Additionally, we will ensure the correctness of IMC controllers. This comprehensive verification will enhance the reliability and correctness of approximate IMC designs.
Supervisor(s): Rolf Drechsler, Chandan Kumar Jha
Host institute: University of Bremen, Germany
Contact person: Rolf Drechsler,
Email: drechsle@uni-bremen.de,
More details at the host webpage:
DC10: Non-ideality tolerant implementation of a model of cortex in a memristor fabric
Description: The Bayesian Confidence Propagation Neural Network (BCPNN) models brain cortex function and supports applications like cortical associative memory and machine learning. Traditional digital BCPNN implementations face bottlenecks, mainly due to synaptic storage and access costs. Memristors, with their non-volatility and efficiency, offer a promising alternative for neuromorphic computing but suffer from nonidealities. This project aims to develop an efficient, scalable BCPNN architecture using memristors. It focuses on leveraging memristor behavior for synaptic computation, supporting diverse BCPNN topologies, enabling brain-like functions such as associative memory, and ensuring resilience against real-world device and circuit limitations.
Supervisor(s): Ahmed Hemani
Host institute: KTH Royal Institute of Technology, Sweden
Contact person: Ahmed Hemani,
Email: hemani@kth.se
More details at the host webpage:
DC11: Neuromorphic system reliability investigations
Description: Neuromorphic systems are gaining increasing attention in modern applications due to their intrinsic ability to mimic brain-like behavior in terms of processing capacity, resilience, self-learning, and self-repair. In recent years, technologies based on emerging memory devices such as RRAM, FeRAM, and MRAM have reached a reasonable level of production maturity, enabling their integration into practical applications. However, their sensitivity to manufacturing process non-idealities makes them prone to in-field faults that can significantly compromise reliability. This Ph.D. project focuses on addressing the reliability challenges associated with AI applications that utilize modern neuromorphic technologies. The research will investigate how manufacturing process variations impact the actual reliability of the final devices and explore mitigation strategies tailored to specific memory technologies. The scope of the project includes the study of existing fault models, reliability assessment methods, and techniques for ensuring in-field dependability of neuromorphic systems.
Supervisor(s): Ernetso Sanchez, Annachiara Ruospo
Host institute: Politecnico di Torino, Italy
Contact person: Ernesto Sanchez, Annachiara Ruospo,
Emails: ernesto.sanchez@polito.it,
annachiara.ruospo@polito.it
More details at the host webpage:
DC12: Sustainable intelligence at the Edge: integrating intermittent computing and neuromorphic architectures
Description: In this project, we will explore the convergence of intermittent computing and neuromorphic systems to enable energy-efficient, resilient edge intelligence. Intermittent computing addresses energy scarcity by allowing systems to operate with sporadic power while retaining state across power failures, ensuring seamless execution. Integrating these with neuromorphic architectures, which mimic brain-like computation, allows for low-power, adaptive processing. Together, they will form a robust framework for always-on, intelligent sensing in constrained environments such as IoT or biomedical devices, where energy reliability is limited but context-aware operation is essential. This synergy promises breakthroughs in sustainable, autonomous edge computing.
Supervisor(s): Domenico Balsamo
Host institute: Newcastle University, UK
Contact person: Domenico Balsamo,
Email: domenico.balsamo@ncl.ac.uk
More details at the host webpage:
DC13: Post-quantum cryptography for emerging computing platforms
Description: Computing systems need to communicate with each other, and public-key cryptography plays a crucial role in establishing secure communication channels between the communicating devices. Post-quantum cryptography or PQC studies novel public-key primitives that prevent quantum computing attacks. PQC schemes rely on mathematical problems that are presumed to be infeasible using classical and quantum computers. Graz University of Technology (TU Graz) is seeking one PhD student for investigations into post-quantum cryptographic security aspects for emerging in-memory computing systems. The ideal candidate for the PhD position will hold a master's degree with project experience in the implementation or mathematical aspects of cryptography.
Supervisor(s): Sujoy Sinha Roy
Host institute: TU Graz, Austria
Contact person: Sujoy Sinha Roy,
Email: sujoy.sinharoy@iaik.tugraz.at
More details at the host webpage:
DC14: FPGA-accelerated emulation framework for self-aware neuromorphic system-on- chip architectures
Description: Current RRAM-based neuromorphic emulators on FPGAs remain limited to device-level characterization and cannot assess full-stack compatibility of self-aware architectures. This PhD will design and validate an FPGA-accelerated emulation framework that maps emerging non-volatile memory, adaptive routing, and on-chip learning mechanisms onto a reconfigurable SoC. By coupling cycle-accurate hardware models with runtime electronics, the platform will deliver in-situ energy, latency, and fault-tolerance metrics thousands of times faster than software simulation. The framework will support early algorithm development, automated design-space exploration, and cross-technology benchmarking, providing unprecedented insight into the co-evolution of hardware and learning rules for future edge-intelligent systems at global scale.
Supervisor(s): Carlos Alberto Valderrama
Host institute: University of Mons, Belgium
Contact person: Carlos Alberto Valderrama,
Email: carlos.valderrama@umons.ac.be
More details at the host webpage:
DC15: CMOS-integrated QRNG for IoT SoC designs
Description: Conventional trusted execution environments for connected sensors struggle with energy-hungry key-generation engines. This PhD will develop a CMOS-compatible quantum random number generator that supplies high-entropy keys to a lightweight TEE suitable for sub- mW Internet-of-Things nodes. The research spans photon shot-noise extraction circuits, robust entropy post-processing, side-channel-resilient interfaces, and statistical validation against NIST SP 800-90B. The QRNG macro will be co-designed with a RISC-V System-on-Chip (FPGA- based) to minimize area, leakage, and start-up latency while enabling remote attestation and secure boot. Silicon prototypes, open-source firmware, and attack-surface characterization will demonstrate provable randomness and lifecycle resilience for mass-market edge devices in ubiquitous resource-constrained deployments.
Supervisor(s): Alessandro Brunetti
Host institute: iQrypto, Belgium
Contact person: Alessandro Brunetti,
Email: a.brunetti@iqrypto.com
More details at the host webpage:
Join the REACT Doctoral Network – Submit Your Application
Dr. Farhad Merchant
REACT Coordinator
Bernoulli Institute & CogniGron
University of Groningen,
The Netherlands
f.a.merchant@rug.nl
F.A. (Farhad) Merchant, Dr | How to find us | University of Groningen